A new modulo 2n+1 multiplier architecture is proposed for operands in the normal representation. The novel architecture is derived by showing that all required correction factors can be merged into a single constant one and by treating this, partly as a partial product and partly by the final parallel adder. The proposed architecture utilizes a total of (n+1) partial products, each n bits wide and is built using an inverted end-around-carry, carry-save adder tree and a final parallel adder.