dc.contributor.author | Τσικρικάς, Ν. | el |
dc.contributor.author | Δρυγιαννάκης, Δ. | el |
dc.contributor.author | Πάτσης, Γεώργιος | el |
dc.contributor.author | Ράπτης, Ιωάννης | el |
dc.contributor.author | Gerardino, Annamaria | en |
dc.date.accessioned | 2015-05-17T17:52:39Z | |
dc.date.available | 2015-05-17T17:52:39Z | |
dc.date.issued | 2015-05-17 | |
dc.identifier.uri | http://hdl.handle.net/11400/10613 | |
dc.rights | Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 3.0 Ηνωμένες Πολιτείες | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/us/ | * |
dc.source | http://www.avs.org/ | en |
dc.source | http://scitation.aip.org/content/avs/journal/jvstb/25/6/10.1116/1.2798714 | en |
dc.subject | Νανοτεχνολογία | |
dc.subject | Δέσμη ηλεκτρονίων | |
dc.subject | Microprocessor chips | |
dc.subject | Τσιπ μικροεπεξεργαστή | |
dc.subject | Εφαρμοσμένη φυσική | |
dc.subject | Nanotechnology | |
dc.subject | Applied physics | |
dc.title | Pattern matching, simulation, and metrology of complex layouts fabricated by electron beam lithography | en |
heal.type | journalArticle | |
heal.classification | Technology | |
heal.classification | Electronics | |
heal.classification | Τεχνολογία | |
heal.classification | Ηλεκτρονική | |
heal.classificationURI | http://id.loc.gov/authorities/subjects/sh85133147 | |
heal.classificationURI | http://id.loc.gov/authorities/subjects/sh85042383 | |
heal.classificationURI | **N/A**-Τεχνολογία | |
heal.classificationURI | **N/A**-Ηλεκτρονική | |
heal.contributorName | Σταυρουλάκης, Σ. | el |
heal.contributorName | Βογιατζής, Ε. | el |
heal.identifier.secondary | DOI: 10.1116/1.2798714 | |
heal.language | en | |
heal.access | campus | |
heal.publicationDate | 2007-12-10 | |
heal.bibliographicCitation | Tsikrikas, N., Drygiannakis, D., Patsis, G., Raptis, I., Gerardino, A. et al. (2007) Pattern matching, simulation, and metrology of complex layouts fabricated by electron beam lithography. "Journal of Vacuum Science & Technology B", 25 (6), p.2307-2311 | en |
heal.abstract | Validation of design rules taking into account fine details such as line-edge roughness, and full chip layout simulation for design inconsistencies, before actual fabrication, are among the main objectives of current software assisted metrology tools. Line-edge roughness quantification should accompany critical dimension (CD) measurements since it could be a large fraction of the total CD budget. A detailed simulation and metrology approach of line-edge roughness quantification versus the length scales in a layout are presented in this work using a combination of electron beam simulation for the exposure part, and stochastic simulations for the modeling of resist film, postexposure bake, and resist dissolution. The method is applied also on a test layout with critical dimension of 200nm and the resulted simulation and scanning electron microscopy images are compared with the aid of a pattern matching algorithm which enables the identification of the desired layout for metrology on a complex layout containing many printed features. | en |
heal.publisher | American Vacuum Society | en |
heal.journalName | Journal of Vacuum Science & Technology B | en |
heal.journalName | JVSTB | en |
heal.journalType | peer-reviewed | |
heal.fullTextAvailability | false |
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