Integrated simulation of line-edge roughness (LER) effects on sub-65nm transistor operation

dc.contributor.author	Πάτσης, Γεώργιος	el
dc.contributor.author	Κωνσταντούδης, Βασίλειος	el
dc.contributor.author	Γογγολίδης, Ευάγγελος	el
dc.date.accessioned	2015-05-18T18:47:03Z
dc.date.issued	2015-05-18
dc.identifier.uri	http://hdl.handle.net/11400/10692
dc.rights	Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 3.0 Ηνωμένες Πολιτείες	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/3.0/us/	*
dc.source	http://proceedings.spiedigitallibrary.org	en
dc.source	http://proceedings.spiedigitallibrary.org/proceeding.aspx?articleid=1323466	en
dc.subject	Photoresistance
dc.subject	Φωτοαντίσταση
dc.subject	Λιθογραφία
dc.title	Integrated simulation of line-edge roughness (LER) effects on sub-65nm transistor operation	en
heal.type	conferenceItem
heal.secondaryTitle	from lithography simulation, to LER metrology, to device operation	en
heal.classification	Technology
heal.classification	Electronics
heal.classification	Τεχνολογία
heal.classification	Ηλεκτρονική
heal.classificationURI	http://id.loc.gov/authorities/subjects/sh85133147
heal.classificationURI	http://id.loc.gov/authorities/subjects/sh85042383
heal.classificationURI	N/A-Τεχνολογία
heal.classificationURI	N/A-Ηλεκτρονική
heal.identifier.secondary	DOI: 10.1117/12.654736
heal.dateAvailable	10000-01-01
heal.language	en
heal.access	forever
heal.publicationDate	2006-03-24
heal.bibliographicCitation	Patsis, G., Constantoudis, V. and Gogolides, E. (2006) Integrated simulation of line-edge roughness (LER) effects on sub-65nm transistor operation: From lithography simulation, to LER metrology, to device operation. "Emerging Lithographic Technologies X". 24 March 2006. San Jose	en
heal.abstract	Understanding how CD metrology, lithographic material and processing, affect linewidth roughness (LWR), and finally device operation is of immense importance in future scaled MOS transistors. The goal of this work is to determine the impact of spatial LWR parameters as well as the relative importance of LWR and CD variation on device operation and to connect material and process parameters with these effects. To this end, we examine first the impact of LWR on threshold voltage shifts by using model lines with fractal self-affine characteristics for the simulation of transistor gate morphology. It is found that for resist lines or transistor gates with constant sigma LWR σLWR, the decrease of spatial LWR parameters (correlation length ξ and roughness exponent α) leads to smaller deviations from the designed electrical transistor performance. Second, the effects of photoresist polymer length and acid diffusion length on LWR parameters and transistor performance are investigated. Through the application of a homemade simulator of the lithographic process, it is shown that photoresists with small polymer chains and small acid diffusion lengths form lines with low LWR parameters (r.m.s. LWR σLWR, ξ ,α) and thus lead to transistors with more reliable electrical performance. Furthermore, the related problem of the relative importance of CD variation and LWR on device operation is addressed. We confirm and generalize the findings of previous works according to which CD variation has more drastic effects on threshold voltage shift than LWR.	en
heal.publisher	SPIE	en
heal.fullTextAvailability	false
heal.conferenceName	Emerging Lithographic Technologies X	en
heal.conferenceItemType	poster