An effective two-pattern test generator for Arithmetic BIST

dc.contributor.author	Βογιατζής, Ιωάννης	el
dc.contributor.author	Ευσταθίου, Κωνσταντίνος Η.	el
dc.contributor.author	Αντωνοπούλου, Σωτηρία-Ήρα	el
dc.contributor.author	Μηλιδώνης, Αθανάσιος	el
dc.date.accessioned	2015-05-21T07:19:20Z
dc.date.available	2015-05-21T07:19:20Z
dc.date.issued	2015-05-21
dc.identifier.uri	http://hdl.handle.net/11400/10818
dc.rights	Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 3.0 Ηνωμένες Πολιτείες	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/3.0/us/	*
dc.source	http://www.sciencedirect.com/science/article/pii/S0045790612001905#	el
dc.subject	Analog CMOS integrated circuits
dc.subject	Built-In Self Test (BIST)
dc.subject	Analog CMOS ολοκληρωμένα κυκλώματα
dc.subject	Two-pattern test generator
dc.subject	Δύο-πρότυπο γεννήτρια δοκιμής
dc.title	An effective two-pattern test generator for Arithmetic BIST	en
heal.type	journalArticle
heal.classification	Computer science
heal.classification	Mathematics
heal.classification	Πληροφορική
heal.classification	Μαθηματικά
heal.classificationURI	http://skos.um.es/unescothes/C00750
heal.classificationURI	http://zbw.eu/stw/descriptor/15045-3
heal.classificationURI	N/A-Πληροφορική
heal.classificationURI	N/A-Μαθηματικά
heal.keywordURI	http://id.loc.gov/authorities/subjects/sh2013002793
heal.identifier.secondary	doi:10.1016/j.compeleceng.2012.10.006
heal.language	en
heal.access	campus
heal.recordProvider	Τεχνολογικό Εκπαιδευτικό Ίδρυμα Αθήνας.Σχολή Τεχνολογικών Εφαρμογών.Τμήμα Μηχανικών Πληροφορικής	el
heal.publicationDate	2013-02
heal.bibliographicCitation	Voyiatzis, I., Efstathiou, C., Antonopoulou, H. and Milidonis, A. (2013). An effective two-pattern test generator for Arithmetic BIST. "Computers & Electrical Engineering", 39(2), February 2013. pp. 398–409. Available from: http://www.sciencedirect.com/science/article/pii/S0045790612001905. [Accessed 20/11/2012]	en
heal.abstract	Built-In Self Test (BIST) techniques perform test pattern generation and response verification operations on-chip. In Arithmetic BIST, modules that commonly exist in datapaths (accumulators, counters, etc.) are utilized to perform the above-mentioned operations. In order to detect faults that occur into current CMOS circuits, two-pattern tests are required. Furthermore, delay testing, commonly used to assure correct temporal circuit operation at clock speed requires two-pattern tests. In this paper a novel two-pattern test generator for Arithmetic BIST is presented. Its hardware implementation compares favorably to the techniques that have been presented in the literature. Application of the proposed scheme for the two-pattern testing of ROM modules revealed that the testing of small-to-medium size ROMs is completed within reasonable time and with negligible hardware overhead.	en
heal.journalName	Computers & Electrical Engineering	en
heal.journalType	peer-reviewed
heal.fullTextAvailability	true