An efficient architecture for accumulator-based test generation of SIC pairs

dc.contributor.author	Βογιατζής, Ιωάννης	el
dc.contributor.author	Ευσταθίου, Κωνσταντίνος Η.	el
dc.date.accessioned	2015-05-24T18:08:17Z
dc.date.available	2015-05-24T18:08:17Z
dc.date.issued	2015-05-24
dc.identifier.uri	http://hdl.handle.net/11400/11059
dc.rights	Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 3.0 Ηνωμένες Πολιτείες	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/3.0/us/	*
dc.source	http://www.sciencedirect.com/science/article/pii/S0026269209000901	en
dc.subject	Stuck-open testing
dc.subject	Two-pattern testing
dc.subject	Κολλημένη-ανοιχτή δοκιμή
dc.subject	Δοκιμών δύο μοτίβο
dc.title	An efficient architecture for accumulator-based test generation of SIC pairs	en
heal.type	journalArticle
heal.generalDescription	Design and Technology of Integrated Systems in the Nanoscale Era	en
heal.classification	Computer science
heal.classification	Computer programming
heal.classification	Πληροφορική
heal.classification	Προγραμματισμός
heal.classificationURI	http://data.seab.gr/concepts/77de68daecd823babbb58edb1c8e14d7106e83bb
heal.classificationURI	http://skos.um.es/unescothes/C00749
heal.classificationURI	N/A-Πληροφορική
heal.classificationURI	N/A-Προγραμματισμός
heal.identifier.secondary	doi:10.1016/j.mejo.2009.05.003
heal.language	en
heal.access	campus
heal.recordProvider	Τ.Ε.Ι. Αθήνας. Σχολή Τεχνολογικών Εφαρμογών. Τμήμα Μηχανικών Πληροφορικής Τ.Ε.	el
heal.publicationDate	2010
heal.bibliographicCitation	Voyiatzis, I. and Efstathiou, C. (August 2010). An efficient architecture for accumulator-based test generation of SIC pairs. Microelectronics Journal. 41(8). pp. 487-493. Elsevier Ltd: 2010. Available from: http://www.sciencedirect.com/science/article/pii/S0026269209000901 [Accessed 12/06/2009]	en
heal.abstract	Research conducted over the years has shown that the application of single input change (SIC) pairs of test patterns for sequential, i.e. stuck-open and delay fault testing is extremely efficient. In this paper, a novel architecture for the generation of SIC pairs is presented. The implementation of the proposed architecture is based on Ling adders that are commonly utilized in current data paths due to their high-operating speed. Since the timing characteristics of the adder are not modified, the presented architecture provides a practical solution for the built-in testing of circuits that contain such adders.	en
heal.publisher	Elsevier Ltd	en
heal.journalName	Microelectronics Journal	en
heal.journalType	peer-reviewed
heal.fullTextAvailability	true