Planar CMOS compatible process for the fabrication of buried microchannels in silicon, using porous-silicon technology

dc.contributor.author	Καλτσάς, Γρηγόριος	el
dc.contributor.author	Παγώνης, Δημήτριος-Νικόλαος	el
dc.contributor.author	Νασιοπούλου, Ανδρούλα Γ.	el
dc.date.accessioned	2015-06-02T12:44:04Z
dc.date.issued	2015-06-02
dc.identifier.uri	http://hdl.handle.net/11400/14816
dc.rights	Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 3.0 Ηνωμένες Πολιτείες	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/3.0/us/	*
dc.source	http://ieeexplore.ieee.org/	en
dc.subject	Buried microchannels
dc.subject	Microfluidic sensor
dc.subject	Porous silicon technology
dc.subject	Θαμμένα μικροκανάλια
dc.subject	Μικρορροϊκός αισθητήρας
dc.subject	Πορώδη τεχνολογία πυριτίου
dc.title	Planar CMOS compatible process for the fabrication of buried microchannels in silicon, using porous-silicon technology	en
heal.type	journalArticle
heal.classification	Technology
heal.classification	Electrical engineering
heal.classification	Τεχνολογία
heal.classification	Ηλεκτρολογία Μηχανολογία
heal.classificationURI	http://id.loc.gov/authorities/subjects/sh85133147
heal.classificationURI	http://zbw.eu/stw/descriptor/18426-4
heal.classificationURI	N/A-Τεχνολογία
heal.classificationURI	N/A-Ηλεκτρολογία Μηχανολογία
heal.identifier.secondary	DOI: 10.1109/JMEMS.2003.820270
heal.dateAvailable	10000-01-01
heal.language	en
heal.access	forever
heal.publicationDate	2003-12
heal.bibliographicCitation	KALTSAS, G., PAGONIS, D.-N. & NASSIOPOULOU, A.G. (2003). Planar CMOS compatible process for the fabrication of buried microchannels in silicon, using porous-silicon technology. Journal of Microelectromechanical Systems. [online] 12 (6). p. 863-872. Available from: http://ieeexplore.ieee.org/	en
heal.abstract	This work presents a new method for the fabrication of buried microchannels, covered with porous silicon (PS). The specific method is a two-step electrochemical process, which combines PS formation and electropolishing. In a first step a PS layer with a specific depth is created at a predefined area and in the following step a cavity underneath is formed, by electropolishing of silicon. The shape of the microchannel is semi-cylindrical due to isotropic formation. The method allows accurate control of the dimensions of both PS and the cavity. The formation conditions of the PS layer and the cavity were optimized so as to obtain smooth microchannel walls. In order to obtain stable structures the area underneath the PS masking layer was transformed into n-type by implantation, taking advantage of the selectivity of PS formation between n- and p-type silicon. With this technique, a monocrystalline support for the PS layer is formed on top of the cavity. Various microchannel diameters with different thickness of capping PS layer were obtained. The process is CMOS compatible and it uses only one lithographic step and leaves the surface of the wafer unaffected for further processing. A microfluidic thermal flow sensor was fabricated using this technology, the experimental evaluation of which is in progress.	en
heal.publisher	IEEE	en
heal.journalName	Journal of Microelectromechanical Systems	en
heal.journalType	peer-reviewed
heal.fullTextAvailability	false