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dc.contributor.author Βογιατζής, Ιωάννης el
dc.contributor.author Ευσταθίου, Κωνσταντίνος el
dc.contributor.author Σγουροπούλου, Κλειώ el
dc.date.accessioned 2015-06-10T23:46:52Z
dc.date.issued 2015-06-11
dc.identifier.uri http://hdl.handle.net/11400/15672
dc.rights Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 3.0 Ηνωμένες Πολιτείες *
dc.rights.uri http://creativecommons.org/licenses/by-nc-nd/3.0/us/ *
dc.source https://www.ieee.org en
dc.subject Memory configuration
dc.subject Διαμόρφωση μνήμης
dc.subject Periodic testing
dc.subject Περιοδικές δοκιμές
dc.title Symmetric transparent online BIST for arrays of word-organized RAMs en
heal.type journalArticle
heal.classification Technology
heal.classification Electronics
heal.classification Τεχνολογία
heal.classification Ηλεκτρονική
heal.classificationURI http://id.loc.gov/authorities/subjects/sh85133147
heal.classificationURI http://id.loc.gov/authorities/subjects/sh85042383
heal.classificationURI **N/A**-Τεχνολογία
heal.classificationURI **N/A**-Ηλεκτρονική
heal.identifier.secondary DOI: 10.1109/DTIS.2013.6527791
heal.dateAvailable 10000-01-01
heal.language en
heal.access forever
heal.publicationDate 2013
heal.bibliographicCitation Voyiatzis, I., Efstathiou, C. and Sgouropoulou, C. (2013) Symmetric transparent online BIST for arrays of word-organized RAMs. "Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era", 2013, p.122-127 en
heal.abstract Transparent BIST schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric Transparent Built-in Self Test (BIST) schemes skip the signature prediction phase required in traditional transparent BIST, achieving considerable reduction in test time. Previous works on symmetric transparent BIST schemes require that a separate BIST module is utilized for each RAM under test. This approach, given the large number of memories available in current chips, increases the hardware overhead of the BIST circuitry. In this work we propose a Symmetric transparent BIST scheme that can be utilized to test RAMs of different word widths; hence, more than one RAMs can be tested in a roving manner. The hardware overhead of the proposed scheme is considerably smaller compared to the utilization of previously proposed symmetric transparent schemes, for typical memory configurations. en
heal.journalName Proceedings of the 2013 8th International Conference on Design and Technology of Integrated Systems in Nanoscale Era en
heal.journalType peer-reviewed
heal.fullTextAvailability false


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Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 3.0 Ηνωμένες Πολιτείες Except where otherwise noted, this item's license is described as Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 3.0 Ηνωμένες Πολιτείες