Implementation of 90 nm CMOS LFSR test vector generator for FPGA floating point arithmetic unit

dc.contributor.author	Noorbasha, Fazal	en
dc.contributor.author	Madhav, Venu C. S.	en
dc.contributor.author	Hu, Jacqueline	en
dc.contributor.author	Harsha Vardhan, GSRK Reddy	en
dc.contributor.author	Rolla, Sireesha	en
dc.date.accessioned	2015-02-11T21:42:50Z
dc.date.available	2015-02-11T21:42:50Z
dc.date.issued	2015-02-11
dc.identifier.uri	http://hdl.handle.net/11400/6069
dc.rights	Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 3.0 Ηνωμένες Πολιτείες	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/3.0/us/	*
dc.source	http://e-jst.teiath.gr/	en
dc.subject	FPAU
dc.subject	IEEE 754
dc.subject	Sticky bit
dc.subject	Round bit
dc.subject	Guard Bit
dc.subject	LFSR
dc.subject	High speed computing
dc.subject	Υπολογιστική υψηλής ταχύτητας
dc.title	Implementation of 90 nm CMOS LFSR test vector generator for FPGA floating point arithmetic unit	en
heal.type	journalArticle
heal.classification	Science
heal.classification	Physics
heal.classification	Επιστήμες
heal.classification	Φυσική
heal.classificationURI	http://zbw.eu/stw/descriptor/15685-2
heal.classificationURI	http://zbw.eu/stw/descriptor/15669-0
heal.classificationURI	N/A-Επιστήμες
heal.classificationURI	N/A-Φυσική
heal.contributorName	Joshi Ram Charan Tej, P.	en
heal.language	en
heal.access	free
heal.publicationDate	2013
heal.bibliographicCitation	Noorbasha, F., Madhav, V.C.S., Hu, J., Harsha Vardhan, GSRK R., Rolla, S., et al. (2013). Implementation of 90 nm CMOS LFSR test vector generator for FPGA floating point arithmetic unit. "e-Journal of Science & Technology". [Online] 8(3): 85-93. Available from: http://e-jst.teiath.gr/	en
heal.abstract	In this paper, we present the LFSR Test Vector Generator for Floating Point Arithmetic Unit (FPAU); it improves the performance of multimedia processing with low hardware cost. Here, we focused on a decimal floating point unit which consists of adder and subtractor for high speed computing. It takes input as binary real numbers, converts them into single precision IEEE 754 format floating point numbers, performs operations and gives the output with high precision. We used Guard bit, Sticky bit and Round bit to get output with good precision. At last, we tested the unit by the values from LFSR. The FPAU was modeled and synthesized in Verilog HDL and LFSR was implemented 90nm CMOS technology.	en
heal.publisher	Νερατζής, Ηλίας	el
heal.publisher	Σιανούδης, Ιωάννης	el
heal.journalName	e-Journal of Science & Technology	en
heal.journalName	e-Περιοδικό Επιστήμης & Τεχνολογίας	el
heal.journalType	peer-reviewed
heal.fullTextAvailability	true