On the design of efficient modular adders

dc.contributor.author	Βέργος, Χαρίδημος Τ.	el
dc.contributor.author	Ευσταθίου, Κωνσταντίνος Η.	el
dc.date.accessioned	2015-03-17T11:03:15Z
dc.date.available	2015-03-17T11:03:15Z
dc.date.issued	2015-03-17
dc.identifier.uri	http://hdl.handle.net/11400/8092
dc.rights	Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 3.0 Ηνωμένες Πολιτείες	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/3.0/us/	*
dc.source	http://www.worldscientific.com/doi/abs/10.1142/S0218126605002726	el
dc.subject	Computer arithmetic
dc.subject	Αριθμητική υπολογιστών
dc.subject	Modular adders
dc.subject	Residue number system
dc.subject	Υπόλοιπο σύστημα αριθμού
dc.subject	VLSI design
dc.subject	Σχεδιασμό VLSI
dc.title	On the design of efficient modular adders	en
heal.type	journalArticle
heal.classification	Computer science
heal.classification	Computer programming
heal.classification	Πληροφορική
heal.classification	Προγραμματισμός
heal.classificationURI	http://data.seab.gr/concepts/77de68daecd823babbb58edb1c8e14d7106e83bb
heal.classificationURI	http://skos.um.es/unescothes/C00749
heal.classificationURI	N/A-Πληροφορική
heal.classificationURI	N/A-Προγραμματισμός
heal.keywordURI	http://id.loc.gov/authorities/subjects/sh85029480
heal.language	en
heal.access	free
heal.recordProvider	Τεχνολογικό Εκπαιδευτικό Ίδρυμα Αθήνας.Σχολή Τεχνολογικών Εφαρμογών.Τμήμα Μηχανικών Πληροφορικής	el
heal.publicationDate	2005-10
heal.bibliographicCitation	Vergos, H. & Efstathiou, C. (2005) On the design of efficient modular adders. Journal of Circuits "Systems, and Computers". 14(5). pp. 965-972.	en
heal.abstract	Modular adders are met in various applications of computer systems. In this paper, we investigate a new architecture for their design that utilizes a carry save adder stage and two binary adders that operate in parallel. Realizations in static CMOS reveal that the introduced architecture leads to modular adder implementations that offer significant savings in delay and power consumption over implementations based on previously proposed architectures. In parallel, the proposed architecture offers significantly smaller implementation area for small operand widths.	en
heal.journalName	Journal of Circuits, Systems, and Computers	en
heal.journalType	peer-reviewed
heal.fullTextAvailability	false