Design of efficient modulo 2n + 1 multipliers

dc.contributor.author	Βέργος, Χαρίδημος Τ.	el
dc.contributor.author	Ευσταθίου, Κωνσταντίνος Η.	el
dc.date.accessioned	2015-03-17T19:48:16Z
dc.date.available	2015-03-17T19:48:16Z
dc.date.issued	2015-03-17
dc.identifier.uri	http://hdl.handle.net/11400/8098
dc.rights	Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 3.0 Ηνωμένες Πολιτείες	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/3.0/us/	*
dc.source	http://digital-library.theiet.org/content/journals/10.1049/iet-cdt_20060026	el
dc.subject	Logic design--Computer programs
dc.subject	Adders
dc.subject	Αθροιστές
dc.subject	Λογική σχεδίαση
dc.subject	Residue number systems
dc.subject	Multiplying circuits
dc.subject	Κυκλώματα πολλαπλασιασμού
dc.title	Design of efficient modulo 2n + 1 multipliers	en
heal.type	journalArticle
heal.classification	Computer science
heal.classification	Computer programming
heal.classification	Πληροφορική
heal.classification	Προγραμματισμός
heal.classificationURI	http://data.seab.gr/concepts/77de68daecd823babbb58edb1c8e14d7106e83bb
heal.classificationURI	http://skos.um.es/unescothes/C00749
heal.classificationURI	N/A-Πληροφορική
heal.classificationURI	N/A-Προγραμματισμός
heal.keywordURI	http://id.loc.gov/authorities/subjects/sh85078118
heal.identifier.secondary	DOI: 10.1049/iet-cdt:20060026
heal.language	en
heal.access	free
heal.recordProvider	Τεχνολογικό Εκπαιδευτικό Ίδρυμα Αθήνας.Σχολή Τεχνολογικών Εφαρμογών.Τμήμα Μηχανικών Πληροφορικής	el
heal.publicationDate	2007-01
heal.bibliographicCitation	Vergos, H. and Efstathiou, C. (2007) Design of efficient modulo 2n + 1 multipliers. IET Computers & Digital Techniques 1(1). pp. 49 – 57.	en
heal.abstract	A new modulo 2n+1 multiplier architecture is proposed for operands in the weighted representation. A new set of partial products is derived and it is shown that all required correction factors can be merged into a single constant one. It is also proposed that part of the correction factor is treated as a partial product, whereas the rest is handled by the final parallel adder. The proposed multipliers utilise a total of (n+1) partial products, each n bits wide and are built using an inverted end-around-carry, carry-save adder tree and a final adder. Area and delay qualitative and quantitative comparisons indicate that the proposed multipliers compare favourably with the earlier solutions.	en
heal.journalName	IET Computers & Digital Techniques	en
heal.journalType	peer-reviewed
heal.fullTextAvailability	false