This paper describes the analysis and modeling of timing and control unit (TCU) for memory processor ALU system, to improve the microprocessor ALU arithmetic and logic operations performance. The system blocks and the behavior of all the blocks are defined and the logical design is implemented in gate level in the design phase. Then the logical circuits are simulated and all of the subunits are converted into FPGA and VLSI CMOS layout. The TCU and Data Stack Swap (DSS) have been integrated in 0.12μm, 90nm CMOS technology. The CMOS logic design is preferred for implement low leakage and high-speed model. In this paper, the functioning of TCU, DSS operations with ALU, the design steps and the obtained results are explained. The main achievement is the implementation is single operations per a single clock cycle as well as double operations per a single clock cycle can perform with respect to select the TCU mode.