VLSI implementation of timing and control unit (TCU) for memory processor ALU system

dc.contributor.author	Noorbasha, Fazal	en
dc.date.accessioned	2015-02-03T16:40:03Z
dc.date.available	2015-02-03T16:40:03Z
dc.date.issued	2015-02-03
dc.identifier.uri	http://hdl.handle.net/11400/5577
dc.rights	Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 3.0 Ηνωμένες Πολιτείες	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/3.0/us/	*
dc.source	http://e-jst.teiath.gr/	en
dc.subject	FPGA
dc.subject	TCU
dc.subject	DSS
dc.subject	ALU
dc.subject	SOR/DOR
dc.subject	CMOS
dc.title	VLSI implementation of timing and control unit (TCU) for memory processor ALU system	en
heal.type	journalArticle
heal.classification	Technology
heal.classification	Electronics
heal.classification	Τεχνολογία
heal.classification	Ηλεκτρονική
heal.classificationURI	http://id.loc.gov/authorities/subjects/sh85133147
heal.classificationURI	http://zbw.eu/stw/descriptor/10455-2
heal.classificationURI	N/A-Τεχνολογία
heal.classificationURI	N/A-Ηλεκτρονική
heal.language	en
heal.access	free
heal.publicationDate	2012
heal.bibliographicCitation	Noorbasha, F. (2012). VLSI implementation of timing and control unit (TCU) for memory processor ALU system. "e-Journal of Science & Technology". [Online] 7(2): 49-55. Available from: http://e-jst.teiath.gr/	en
heal.abstract	This paper describes the analysis and modeling of timing and control unit (TCU) for memory processor ALU system, to improve the microprocessor ALU arithmetic and logic operations performance. The system blocks and the behavior of all the blocks are defined and the logical design is implemented in gate level in the design phase. Then the logical circuits are simulated and all of the subunits are converted into FPGA and VLSI CMOS layout. The TCU and Data Stack Swap (DSS) have been integrated in 0.12μm, 90nm CMOS technology. The CMOS logic design is preferred for implement low leakage and high-speed model. In this paper, the functioning of TCU, DSS operations with ALU, the design steps and the obtained results are explained. The main achievement is the implementation is single operations per a single clock cycle as well as double operations per a single clock cycle can perform with respect to select the TCU mode.	en
heal.publisher	Νερατζής, Ηλίας	el
heal.publisher	Σιανούδης, Ιωάννης	el
heal.journalName	e-Journal of Science & Technology	en
heal.journalName	e-Περιοδικό Επιστήμης & Τεχνολογίας	el
heal.journalType	peer-reviewed
heal.fullTextAvailability	true