Νovel modulo 2n + 1 multipliers

dc.contributor.author	Βέργος, Χαρίδημος Τ.	el
dc.contributor.author	Ευσταθίου, Κωνσταντίνος Η.	el
dc.date.accessioned	2015-03-17T11:16:22Z
dc.date.available	2015-03-17T11:16:22Z
dc.date.issued	2015-03-17
dc.identifier.uri	http://hdl.handle.net/11400/8094
dc.rights	Αναφορά Δημιουργού-Μη Εμπορική Χρήση-Όχι Παράγωγα Έργα 3.0 Ηνωμένες Πολιτείες	*
dc.rights.uri	http://creativecommons.org/licenses/by-nc-nd/3.0/us/	*
dc.source	http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1690036&abstractAccess=no&userType=inst	el
dc.subject	Logic design
dc.subject	Adders
dc.subject	Αθροιστές
dc.subject	Carry logic
dc.subject	Λογική Carry
dc.subject	Λογική σχεδίαση
dc.subject	Multiplying circuits
dc.subject	Κυκλώματα πολλαπλασιασμού
dc.subject	Trees (mathematics)
dc.subject	Δέντρα (μαθηματικά)
dc.title	Νovel modulo 2n + 1 multipliers	en
heal.type	conferenceItem
heal.classification	Computer science
heal.classification	Computer programming
heal.classification	Πληροφορική
heal.classification	Προγραμματισμός
heal.classificationURI	http://data.seab.gr/concepts/77de68daecd823babbb58edb1c8e14d7106e83bb
heal.classificationURI	http://skos.um.es/unescothes/C00749
heal.classificationURI	N/A-Πληροφορική
heal.classificationURI	N/A-Προγραμματισμός
heal.keywordURI	http://id.loc.gov/authorities/subjects/sh85078117
heal.identifier.secondary	DOI: 10.1109/DSD.2006.71
heal.language	en
heal.access	free
heal.recordProvider	Τεχνολογικό Εκπαιδευτικό Ίδρυμα Αθήνας.Σχολή Τεχνολογικών Εφαρμογών.Τμήμα Μηχανικών Πληροφορικής	el
heal.publicationDate	2006
heal.bibliographicCitation	Vergos, H. & Efstathiou, C. (2006) Νovel modulo 2n + 1 multipliers. in ''9th EUROMICRO Conference on Digital System Design (DSD΄06)'', pp. 168-175, Dubrovnik 2006.	en
heal.abstract	A new modulo 2n+1 multiplier architecture is proposed for operands in the normal representation. The novel architecture is derived by showing that all required correction factors can be merged into a single constant one and by treating this, partly as a partial product and partly by the final parallel adder. The proposed architecture utilizes a total of (n+1) partial products, each n bits wide and is built using an inverted end-around-carry, carry-save adder tree and a final parallel adder.	en
heal.fullTextAvailability	false
heal.conferenceName	9th EUROMICRO Conference on Digital System Design (DSD΄06)	en
heal.conferenceItemType	full paper